Currently, on-chip memories may consume a large area in system on chip. In general, the system on chip memories, such as a SRAM (Static Random Access Memory) may be used for different levels of cache memories, a ROM (Read only Memory) may be used in processors for storing instruction set, and a RF (Register Files) may be used within multi-core processors. Further, the memory chip such as SRAM, ROM, and RF may include at least two types of hardware circuits such as bit-cell array circuits and periphery circuits. The bit-cell array may circuits include an array of bit-cells, which store 1-bit of data in each cell and the periphery circuits may include logic gates to control read and write operations. In general, fin-FET (fin-Field Effect Transistor) technology may have performance issues with respect to on-chip memories. For example, device gate capacitance may be high compared to planar CMOS (Complementary Metal Oxide Semiconductor) nodes, wherein the nodes (also technology nodes, process node, process technology or simply node) refer to a specific semiconductor manufacturing process and its design rules. In another example, resistance may be much higher in advanced nodes such as finFET, which may limit the overall performance of the SoC. In yet another example, an area of memory may be limited by width of metal tracks, wherein the metal tracks may be used to transmit the address signals, clock signals and so on. Accordingly, the performance of on-chip memory (such as SRAM, RF or ROM) may be determined by at least one of cycle time and access time. The access time may also include the time for decoding a word-line.